Hardware Engineering, Sr Staff Engineer

September 4, 2024

Synopsys

新竹市

52143BR

TAIWAN - Hsin Chu Science Park

Job Description and Requirements

Job Description & Requirements

Job Description and Requirements
Synopsys is uniquely positioned to offer the most comprehensive prototyping solution in market today. HAPS system is the prototyping solution of Synopsys ASIC validation flow, it’s the industry’s performance & capacity leader in prototyping.

As a hardware designer, candidate will be primarily responsible for successful deployment of HAPS related board design including its validation. He or she will closely work with AE and customers to propose and design/validate protocol interface card solution on HAPS which can be a reference design kit.

Candidate should be also able to investigate/understand schematics and layout of HAPS daughter board to debug any PCB issues. The position offers a great opportunity not only to grow by learning kinds of peripheral interface solution but also communication skills and project management capability from Synopsys.

Education Requirements
- College degree(or above) in Electrical Engineering/ Computer Science related
Skills/Experience
- Good team player and communication skills
- Good experience on porting RTL to FPGA using Vivado or Synplify/Protocompiler/Protosynthesis or 3rd party FPGA synthesizer
- Good expertise on one of the following FPGA prototyping platforms such as HAPS/S2C/Talent Pros etc. where with related FPGA compile/runtime/debug experience is appreciated and preferred
- Familiar with one of following protocols: MIPI/HDMI/AMBA/USB/PCIE/DDRx etc.
- Experience on Driver/FW/SOC FPGA debug/development
- Familiar with simulation and debug tools such as VCS and Verdi/LINT
- Familiar with scripting language like Perl/Python/Tcl/CSH/BASH/Makefile
- Fluent English on reading/writing (esp. technical spec)
Nice to have
- Experience on hardware board design tools such as Orcad/PADS and Allegro
- Experience on multi FPGA partition with well timing constraint knowledge
- Experience on Xilinx high speed IO application such as using GTH/GTY
- Experience on Xilinx EDK/Vitis development tools