Job Opportunities in Israel

What will your job look like:

• Leading Full Chip Layout activities & methodologies for a brand new So C, from definition to Tape Out.
• Floor Planning Top to Bottom & Bottom up - FC, Sub System & Block level.
• IO Pad, Bump, RDL & ESD planning & implementation, co-designing with Package & Board.
• Involved in chip architecture, in close collaboration with the design & architecture teams.
• Exploring different floorplan structures to achieve both best area & ease of convergence.
• Physical verification owner, defining Physical Verification methodologies & activities for Full Chip, Sub System & Block Level.
• Working with engineers to identify and overcome roadblocks and obstacles.

All you need is:

• BSc/MSc in Electrical Engineering/Computer Science.
• 8 years of experience in VLSI backend (RTL2GDS).
• 5 years of experience in Full Chip Integration & verification on complex So Cs.
• Expert knowledge in floor planning, integration & signoff methodologies for hierarchical designs.
• Physical Verification Expert (DRC/LVS/PERC).
• Experience with IO Pad, Bump & ESD planning.
• Experience in technically leading complex backend activities, preferably of complete So C's.
• Expert knowledge of the entire backend design flow from RTL to TO. (Synthesis, FP, Pn R , CTS , STA, EM/IR, Chip Integration & Physical Signoff).