Job Opportunities in Poland
October 15, 2024
Synopsys
Gdańsk
A&MS Layout Design Engineer
In this role you will collaborate in the development of advanced analog integrated circuit designs using best-in-class Synopsys suite of tools. You will be working with local and global teams in developing layout for complex mixed-signal designs in the latest technology nodes.
As a member of our Solutions IP Design Group you will be developing IP in various technology nodes and foundries for different customers in a fast paced and exciting design environment.
Main Requirements:
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
Our Silicon IP business is all about integrating more capabilities into an So C—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.
As a member of our Solutions IP Design Group you will be developing IP in various technology nodes and foundries for different customers in a fast paced and exciting design environment.
Main Requirements:
- Master´s or Bachelor´s degree in Electronic/ Electric engineering with a strong interest to develop within the area.
- Good understanding of basic electric rules (ie. resistance, capacitance, inductance)
- Familiarity with silicon physical phenomena and basic active silicon devices behavior
- A quick learner and a problem-solver
- Good written and verbal English skills
- Familiarity with layout of analog and mixed signal CMOS circuits
- 1+ year of a relevant work experience
-
Experience in the following layout design techniques:
- Optimization for signal integrity (ie. clock/data routes, differential routing, shielding)
- Implementation of ESD design constraints, latch-up risk mitigation
- Familiarity with custom digital layout (logic cell layout and associated logic path routing)
- Layout design for reliability (ie. EM, IR, etc…)
- Design to optimize for parasitic layout effects (ie. matching, reliability, proximity effects, etc…)
- Full custom analog layout design tool: Custom Compiler (or equivalent)
- Verification tools: ICV, Calibre, Star-RCXT, PERC
- Experience in working with Jira/Atlassian (or other such) tools
- Exposure to scripting (ie. TCL, PERL, etc…)
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
Our Silicon IP business is all about integrating more capabilities into an So C—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.
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