Our Digital ASIC Design Team is currently seeking candidates who will be responsible for the implementation and verification of advanced DFT/DFD (Design for Test/Design for Debug) techniques for low-power, multi-voltage designs.
The successful candidate will help deploy DFT methodologies that reduce test costs, increase product quality, and enhance yield learning on leading-edge process technologies. The candidate should understand digital logic design topics such as combinational and sequential circuits, Finite State Machines (FSMs), clocking, and setup/hold times. Any coursework undertaken in the field of testing of VLSI circuits will be an added plus.
Job responsibilities include DFT pattern generation, coverage analysis, and debugging as well as running and debugging gate-level simulations.
All employees are expected to support diversity within their teams and throughout the company.
Preferred Qualifications:
- Master’s or Bachelor’s degree in Electrical or Computer Engineering.
- Understanding of digital logic design and verification.
- Familiarity with System Verilog, UVM, and use of assertions during verification.
- Proficiency in Perl, Python, or other scripting languages.
- Exposure to EDA tools is considered advantageous.
- Detail-oriented with strong organizational, problem-solving, and communication skills.
- Good team player.