In this role you will be responsible to model, analysis and estimate power consumption of daily use cases on our next generation So Cs. Drive new ideas into micro-architecture, design and circuits to reduce So C power across the dynamic range. Drive budgeting, measurement and analysis of overall So C power for many use cases of interest. You Will work extensively with many teams across every stage of the project from Architectural definition through Design implementation and SW management to focus on power optimization. To be successful in this role, you must have keen interest and motivativation to deliver best experience to our users, and wide perspective in order to work simultaneously on multiple disciplines. This role is required working closely with many cross-functional teams and good understanding of hardware and software interaction at system level.
Description
In this highly visible role, you will be responsible for SOC power simulation and power modeling, SOC use case power analysis, and drive the future SOC power optimization. BS.c in EE / MS.c in EE or Computer Science/ Electrical Engineering required.
Key Qualifications
Experience in SOC power simulation and modeling
Experience with ASIC power analysis and optimization
Strong understanding of power tradeoffs at the architectural, logic design, and physical design levels
Understanding of SOC design flow and methodology
Strong interpersonal skills are a pre-requisite as you will collaborate with many different groups
Preferred Qualifications
Preferred Qualifications
MS.c in Electrical Engineering
Silicon power measurement experience
Familiarity multimedia data processing
Coding in Python
Familiarity with Verilog and System Verilog
Education & Experience
BS.c in EE / MS.c in EE or Computer Science/ Electrical Engineering required.
Additional Requirements
We regret to inform you that this job opportunity is no longer available