Wiliot was founded by the team that invented one of the technologies at the heart of 5G. Their next vision was to develop an Io T sticker, a computing element that can power itself by harvesting radio frequency energy, bringing connectivity and intelligence to everyday products and packaging, things previously disconnected from the Io T. This revolutionary mixture of cloud and semiconductor technology is being used by some of the world’s largest consumer, retail, food, and pharmaceutical companies to change the way we make, distribute, sell, use, and recycle products. Our investors include Softbank, Amazon, Alibaba, Verizon, NTT Do Co Mo, Qualcomm, and Pepsi Co. We seek a highly skilled Silicon Digital Design and Micro-Architecture Engineer with technical lead abilities to join our Mix Signals Silicon development group. In this pivotal role, you will lead the design, and micro-architecture activity for our next-generation mixed signal cutting-edge So C-based device. Your expertise in design, microarchitecture, and technical leadership capabilities will be instrumental in driving the innovation of our next-generation product.
Requirements:
BCs in Electrical Engineering.
Minimum 7 years of experience in Silicon/So C design, with a microarchitecture development knowledge
Experience in leading design teams and So C integration and execution.
Deep understanding of So C microarchitecture and integration and UPF flows.
Experience with PPA analysis tools and techniques, such as simulation, profiling, and benchmarking.
Strong problem-solving and analytical skills, with the ability to identify and resolve complex technical challenges.
Excellent communication and interpersonal skills, with the ability to effectively collaborate with cross-functional teams.
Extensive Knowledge of Verilog RTL, SV-UVM, UPF, CPU (RISC-V), and FW code.
Advantages: knowledge of MCU So C Arch. , Analog ICs, and Lab equipment.
Preferred Qualifications:
Experience with ultra-low power design methodologies.
Familiarity with MCU Architecture and RISC-V ISA.
Familiarity with Analog ICs such as DCDCs , clock sources, Sensors, and clock sources.
A passion for innovation and a drive to push the boundaries of what is possible in So C design.
If you are a highly motivated and talented individual with a proven track record in Silicon/So C design and u-Architecture, we encourage you to apply for this exciting opportunity.
Responsibilities:
Technical Leadership: Provide technical guidance and mentorship to a team of talented engineers, ensuring efficient collaboration with the analog, system, verification, and physical teams. and help deliver high-quality designs.
Design and Micro-Architecture responsibilities: Help define and execute (hands-on) the design and microarchitecture activity, low-power So Cs, considering factors of power, performance, Area (PPA). Including documentation and reviews.
Power and Area Optimization: Analyze and optimize the PPA of the So C, Design and implement power-saving techniques using UPF flow and Power estimation tools.
So C activity: Collaborate with cross-functional teams to plan, execute, and track project timelines.