SENIOR VERIFICATION ENGINEER – SV UVM Smart So C is looking for smart and enterprising Design Verification engineers to come to join us and get an opportunity to do some cutting-edge work and also work in a great environment where work is Always Fun and Exciting. Smart So Cs is currently working on multiple in-house turnkey projects and client site projects and many of our projects involve complete verification from spec to closure including building complete DV environments in SV-UVM. Job Responsibilities-
Build SV, SV UVM, OVM based environments.
Work with many different networking and other protocols
Desired Skills and Experience-
3 to 10 years of experience in IP verification
Good experience in SV/ UVM based verification project. Good debug skills is a must.
Experience in building components like Scoreboard, functional coverage & writing sequences using SV/UVM based Verification environment
One of the following experiences is important:
Experience in Video/Display domain in particular DP, o LDI, MIPI CSI/ DSI
Experience in any one high speed protocol like USB3, PCIe, MIPI, Unipro etc
Job Category: VLSI (Silicon engineering)
Job Location: Finland: Oulu India: Bangalore India: Chennai India: Hyderabad India: Noida Malaysia Singapore Sweden: Stockholm USA: Delaware
We regret to inform you that this job opportunity is no longer available